"Do not mix topologies for outputs. They are all either sinking or sourcing per connector (X16 / X17)." p.103 should be X15/X16.
Please redraw diagram on p.104 to clarify input and output commons. Typical usage in my experience has been to implement a single topology (i.e. all PNP or all NPN, not split between PNP/NPN inputs and outputs). As it is, descriptions for pins 11/29 on X15/X16 are confusing (COM_EMT and COM_COL imply opposing terminals of a transistor yet both diagrams on p.104 show them connected to the same reference voltage).
