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Hardware (encoder) position - compare function with Power PMAC


qchen3
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For the hardware position compare function in the Power PMAC, as stated in the manual,

(1) The CompA and CompB specify the raw encoder encoder position at which a position-compare event will take place. It is in the units of 1/4096 of a count of the encoder.

(2) When the instantaneous encoder position matches that of the preset CompA & CompB registers, the “EQU” compare digital output is toggled. This function is executed in hardware.

 

The question is:

If a sin/cos encoder is used, is the 1/4096 sub counts generated in hardware? If not, then the execution still has the software intervention since the instantaneous encoder feedback is generated in software.

 

The reason to ask this question is because we have observed significant amount of “EQU” output pulse jitter at the constant velocity motion condition. The amount of position error in our motion system only accounts for small portion of this jitter. We need to find out the main contribution factor.

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For purposes of the compare function, the subcount estimation is generated by timer circuits in the ASIC using the ratio of the time since the last zero crossing (hardware count) of the sine or cosine signals and the time between the last two zero crossings. Make sure that Gate3.Chan[j].TimerMode is set to its default value of 0 to enable this timer-based sub-count estimation.

 

Typically, the biggest source of error in this technique comes from uneven spacing of the zero crossings, which can be due to voltage offsets, phase offset, or magnitude mismatch in the sine/cosine signals. These distort the ratio calculations of this estimation.

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The statement on Gate3.Chan[j].TimerMode in the User's Manual (page 473) is what exactly confused me:

 

(1) " All 3 elements are unsigned 32-bit integer values, in units of 1/4096 of a count of the encoder. That is, they have 20 bits of full-count information, and 12 bits of fractional-count information."

(2) "If saved setup element Gate3.Chan[j].TimerMode is set to its default value of 0, “hardware 1/T” count extension is enabled for the channel to calculate an estimated fractional-count value every SCLK cycle. The IC can then compare the combined whole-count and fractional-count value against the values in the compare registers, which have 24 bits of whole-count data and 8 bits of fractional data."

 

Which fractional-counts is used then: 12 bits or 8 bits?

 

Initially, I thought 12bits fractional-counts is for sinusoidal encoder, 8bits is for quadrature encoder. Since a sinusoidal encoder is used for my case (Gate3.Chan[j].AtanEna=1), I thought the setting of TimerMode does not matter.

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There are a lot of different things going on, so it can get confusing. That paragraph was badly written (thanks for pointing it out). The paragraph above it is correct in specifying 12 bits of fraction in the compare registers.

 

If TimerMode is set to 0, the ASIC is calculating timer-based sub-count estimation with 12 fractional bits. Not all of these bits are available in all registers in all modes. If AtanEna is set to 0, the ServoCapt, PhaseCapt, and HomeCapt registers only latch the first 8 bits of this information, as this is enough resolution for almost all users, and provides 24 bits of whole-count information in the 32-bit register. (Note that in this mode, the TimerA register has 12 bits of fraction latched on the servo clock, and TimerB has 12 bits of fraction latched on the input trigger.)

 

If AtanEna is set to 1, the ServoCapt and PhaseCapt registers have 12 bits of fractional count resolution from the A/D registers through the arctangent function. (This is 14 bits of fraction per line, for a x16384 interpolation.)

 

The CompareA, CompareB, and CompareAdd registers always have 12 bits of fractional data. The added resolution is particularly useful for the CompareAdd register, even if not needed for individual compare events. The subcount estimation used to compare against these registers is from the timers (when TimerMode = 0), even if AtanEna is 1. The A/D converters cannot be sampled often enough to be useful for compare purposes.

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