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2 ACC5Es, Asynchronous Phase Clocks?


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Is it possible to use 2 ACC5Es in a single UMAC rack (or 2 ACC5E3s) in order to get 2 MACRO rings that are running at different phase clock rates? I believe the answer is yes, but I just wanted to double check.


Each 5E would be connected to a separate MACRO ring of course. We would like to run the first ring at 18-27 kHz and the second ring at 40-50 kHz.

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To answer this first we have to note that all accessories on a UMAC backplane or a PMAC with embedded DSPGates should run at the same phase/servo frequencies or at least at integer multiplication of a base phase/servo frequency. I had made a spreadsheet for the proper calculations in a Turbo PMAC system for achieving different PWM frequencies from different DSPGates, but it is still relevant to this topic so I'll share it here.


Multiple PWM clock calculator.xls


Using ACC-5E, which is developed based upon DSPGate2 architecture, all of the phase tasks will be performed upon the internal phase clock if the DSPGate is the source of the clock (I6807 or gate2.PhaseServoDir ) or external clock if the DSPGate is receiving the clocks. The phase tasks include all of the MACRO ring communication activities. This means all ACC-5E devices on a UMAC rack will have exact same MACRO frequency.


Using ACC-5E3, which is developed based upon DSPGate3 architecture, although all DSPGate3 receive and share the same phase and servo frequency on the backplane, each DSPGate3 can have it's own internal Phase clock which is phase lock looped to the external one and it is an integer multiplication of it. This allows you to have 2 separate MACRO frequencies on 2 separate rings.


Notice that the CPU will only run at one of the frequencies and the other ring will either skip some of the commands which are being sent from the CPU or it will be re-transmitting the previous command depending on whether it is running slower or faster than the CPU respectively.


It is important to note that the calculations for Ring Error Check Period have to be carefully looked at since they are designed to work with only a single ring frequency.

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Do you have a similar spreadsheet for the DSPGATE3s?


If I'm understanding you correctly, we can have 2 ACC5E3s in a single UMAC rack, as long as the phase clocks are integer multiples.


Here is what we are trying to do specifically:


DSPGATE3 #1 and #2 -

27 kHz Phase clock (for MACRO ring #1)

9 kHz PWM


DSPGATE3 #3 and #4 -

54 kHz Phase clock (for MACRO ring #2)

9 kHz PWM


Power PMAC -

27 kHz phase interrupt


Is this possible using ACC5E3s? It is very important that we can keep the Power PMAC phase interrupt at 27 kHz even though the max DSPGATE3 freq. is 54 kHz.

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