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SPI encoder protocol support on Gate3


jbeasley
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There is some information that SPI is option 1 on the encoder support table but seems to have been omitted from the printed documentation. Was this implementation also removed from the firmware? Did it support the Chip Select portion of the protocol and what was the pinout on the PowerBrick connectors? I realized noise immunity is a problem but I'm just poking around at this point.

 

I was playing around with a CUI absolute encoder that states it's SSI but in fact is some variation of SSI that resembles SPI on the hardware level with CS low for addressing the module and single ended data and clock. I was going to look at using a differential line driver to convert the single ended Data and Clock to RS422 specifications but it's pointless if I don't have the CS cycled low during the transmission.

 

I'm also looking at using an FPGA to interface with the 3 wire SSI and then send that data over to the Power Brick with Standard SSI but this adds another layer of complexity I would rather avoid if possible.

 

Thanks

John.

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See the “Power PMAC User’s Manual” page 128. See also the “Power PMAC Software Reference Manual” page 381.

 

There were not any well known commercial SPI encoders to document at the time. The most common usage is with The ACC-24E3 ACI interpolator to access the “Signal Error Auto-Detection and Correction” FPGA data directly. This is documented in the ACC-24E3 manual, see the section “Reading the Data as a Serial-Interface Position Value” starting on page 60.

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