Edge detection fail in Capture/Compare Interrupt Service Routine

[RafaelFalcaro]

Hello, I'm using PowerPMAC's ISR interrupt to perform axes position acquisition, with the trigger source being the UserFlag signal.

The implementation is functional, however the interrupt is being executed at each edge of the trigger, regardless of its direction (rising or falling).

I would like the interrupt to happen only on the falling edge of the UserFlag signal. Here are the settings I made:

Gate3[0].IntCtrl = $10000
Gate3[0].Chan[0].CaptCtrl = 10
Gate3[0].Chan[0].CaptFlagSel = 3
Gate3[0].Chan[0].CaptFlagChan = 0
UserAlgo.CaptCompIntr = 1

Here is the code inside the ISR:

void CaptCompISR (void)
{
	volatile GateArray3 *MyFirstGate3IC; // ASIC structure pointer
	int *CaptCounter; // Logs number of triggers
	int *CaptPosStore; // Storage pointer
	MyFirstGate3IC = GetGate3MemPtr(0); // Pointer to IC base
	CaptCounter = (int *)pushm + 65535; // Sys.Idata[65535]
	CaptPosStore = (int *)pushm + *CaptCounter + 65536;
	*CaptPosStore = MyFirstGate3IC->Chan[0].HomeCapt; // Store in array
	(*CaptCounter)++; // Increment counter
	MyFirstGate3IC->IntCtrl = 1; // Clear interrupt source
}

 

[Sangmo]

You can check the bit11 of Gate3[i].Chan[j].Status after entering the ISR function.

If bit11 is 0, it means that the edge signal that triggers the interrupt is a falling edge.

 

[RafaelFalcaro]

Hi @Sangmo, thanks for the reply!

 

So I understand that the ISR function is executed on any edge of my trigger signal, is that right?
I'm asking because in the Power PMAC User Manual (page 787) there is an information that for PMAC3-style ICs the detection is done via “edge-triggered” capture logic:

 

 

If this is correct, what is the need to configure the Gate3[0].Chan[0].CaptCtrl register, since it only matters which trigger source (Gate3[0].Chan[0].CaptFlagSel)?

 

Edited March 6, 2023 by RafaelFalcaro

[steve.milici]

Logic based on the value bit11 in Gate3[i].Chan[j].Status would need to be added to the ISR.

[rleoni]

Hello, 

I am working with Rafael on this issue and we solved the edge detection problem by setting Gate3[0].EncClockDiv.

[steve.milici]

Good to know ... I should have suspected that!😬

[rleoni]

@steve.milici

did some tests to validate the maximum input frequency in the "user flag" that I can trigger the ISR and it is significantly lower than when I use the encoder index. You know why?
Is there any difference in the detector circuit?


User flag/home flag: ~12,5kHz
Index encoder: ~50kHz

PS: I' using Power Brick LV-IMS. 

Edited March 21, 2023 by rleoni

[steve.milici]

There is the option to have the flag inputs further filtered by a second digital delay filter whose propagation is controlled by a clock frequency determined by Gate3[i].FiltClockDiv.