ACC28E example

[bradp]

This is a CPLC example to read the data from an ACC28E and place the results into P-variables. #include #include #include void user_plcc() { int AD1, AD2, AD3, AD4; volatile unsigned *pACC28E; pACC28E = GetIOMemPtr(); // pointer to I/O boards // divide by 4 to get the correct offset from the base io memory pointer // ACC28E at chip select 10 all switches closed AD1 = (*(pACC28E + 0xa00000/4 + 0))/65536; AD2 = (*(pACC28E + 0xa00000/4 + 1))/65536; AD3 = (*(pACC28E + 0xa00000/4 + 2))/65536; AD4 = (*(pACC28E + 0xa00000/4 + 3))/65536; pshm->P[1] = (double) AD1; pshm->P[2] = (double) AD2; pshm->P[3] = (double) AD3; pshm->P[4] = (double) AD4; // ACC28E at chip select 11 all switches closed except switch one is open AD1 = (*(pACC28E + 0xb00000/4 + 0))/65536; AD2 = (*(pACC28E + 0xb00000/4 + 1))/65536; AD3 = (*(pACC28E + 0xb00000/4 + 2))/65536; AD4 = (*(pACC28E + 0xb00000/4 + 3))/65536; pshm->P[5] = (double) AD1; pshm->P[6] = (double) AD2; pshm->P[7] = (double) AD3; pshm->P[8] = (double) AD4; }

[dzrong]

Can we use Encoder Conversion Table to make the data from ACC-28E as feedback ? Because the data from PLC will make the delay! Thanks!

[Sina.Sattari]

[quote='dzrong' pid='369' dateline='1270712580'] Can we use Encoder Conversion Table to make the data from ACC-28E as feedback ? Because the data from PLC will make the delay! Thanks! [/quote] You can use the Encoder Conversion Table type 1 entry in order to read ACC-28E or any parallel type of memory location. Here is the settings you need to have in order to read the first channel of an ACC-28E (SW1 all in CLOSE position). In current released firmware, you have to manually set the address. In future firmwares, you will have structure name of [b]Acc28E[0].SAdc[0].a[/b] for addressing purpose. [code]EncTable[1].Type=1; EncTable[1].pEnc=Sys.piom+$A00000; EncTable[1].Index2=16; EncTable[1].Index1=16;[/code] The base address of the Acc-28E can be found in [url=http://forums.deltatau.com/showthread.php?tid=85]THIS POST[/url] under [b] Power PMAC Address Offsets 2009-08.pdf [/b] [b]Type[/b] 1, defines 32 bit parallel read from a memory location pointed by [b]pEnc[/b]. The date first will be right shifted by [b]Index2[/b] bits (to clear any data that might be in lower 16 bits) and then left shifted by [b]Index1[/b] bits which will set the MSB of data which has the sign bit to bit 31 of result word.