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ACC-14M Analog Input sampling frequency


coles55
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Hello,

Is there anyway to control the sampling rate on the ACC-14M? The manual indicate a Burr-Brown ADS8361 which samples at 500kHz maximum frequency. Which clock does the ADC use on the ACC-14M and is this clock adjustable? We are using the ACC-5E3 to communicate with the ACC-14M.

 

Thanks,

Lei

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The ADC sampling rate is controlled by the phase clock on the Slave station, which is governed by MI992 and MI997.

 

You should set your slave's phase clock to be identical to the phase clock on the Master station. So, if you want to change the phase clock on the slave, you have to change it on the Master as well. The following structures affect clocks on the Master:

 

Acc5E3[0].PhaseFreq

Acc5E3[0].ServoClockDiv

Acc5E3[0].PhaseClockDiv

Acc5E3[0].PhaseClockMult

 

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Charles,

Is there any limitation in terms of the clock rate I can run at on the ACC-5E3 (in this case the Macro Master)? The manual indicate that the values for the Acc5E3[0].PhaseFreq ranges from 35.76 Hz to 2,343,463 Hz. However, when I increased the phase frequency to above 10kHz, the analog readings froze. At the same time, I would think there is a limitation on the clock rate of the ACC-14M as well. Since the ACC-14M has 2 Burr-Brown ADCs that samples at 500kHz at max speed, we would like to run at this speed.

 

Thanks,

Lei

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If you change the phase frequency on your Master (ACC-5E3), you must also change it on your Slave (ACC-14M). If you have not done this, I would expect problems.

 

The degree to which you can increase your phase frequency depends on the task load the Master's CPU experiences. You can observe the CPU loading in the Task Manager (in the IDE, click Tools-->Task Manager). Click the Tasks tab in the Task Manager to see the task distribution:

 

taskmanager.png.8644d629bbd1d2e39030b77ae3c68ff7.png

 

If it appears your phase task overwhelms the CPU to the point that the other tasks cannot complete in time, your CPU will probably WatchDog and completely freeze.

 

I do not recommend setting the phase frequency to 500 kHz. The highest you probably want to go is 24 kHz in order to be able to safely finish all of the other tasks inside PMAC.

 

Remember the Nyquist Sampling Theorem: you only need your sampling frequency to be at least twice that of the frequency of the signal you want to sample. So if your signal is 5 kHz, you only need a 10 kHz phase clock.

 

EDIT: Addition: You cannot exceed 20.833 KHz for these ADCs. This is from a few limitations. The first limitation is the ADC clock rate (0.5 MHz) for this product. This leads to the next limitation that is the maximum rate at which it can be sampled. The data is sampled during the phase clock. When the phase clock goes from low to high, it is strobed and then the data must be latched by the time phase clock goes from high to low:

 

latch.thumb.png.c7a9bacb0a9ebe0b7cfd92d1ff08ff04.png

 

The data from the ADC comes from a 24-bit register and each bit will be processed every ADC clock cycle. Therefore, it will take a minimum of 24 ADC clock cycles to return the proper ADC value to the PMAC. So, if we are limited to 0.5 MHz ADC clock and it takes 24 cycles to read the data, then the minimum of 48 µsec* is needed to read the data. The 48 µsec represents the time from the strobe to the latch of the phase clock. To have a phase clock on time of about 48 µsec, set the phase clock to about 20.833 KHz. 20.833 KHz is the maximum phase clock frequency that can be set in the PMAC2 when using this product.

 

*The 48 µsec is calculated by taking 0.5 Mhz/24 cycles.

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Hi I am working with Lei. If we are running multiple 14M's on the fiber ring connected to the 5E and each 14M has two Analog signals coming back on it, do we have to divide this capture rate accordingly? For Example (2) 14M's x (2) signals each = 20.83KHz/ (2*2)?

 

Thanks,

Joe

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