Jump to content
OMRON Forums

How to setup ACC36E on UMAC MACRO STATION with PPMAC


dzrong
 Share

Recommended Posts

Hello Everyone,

 

In the new manual of ACC36E,I know how to setup ACC36E in some stuation:

USING ACC-36E WITH UMAC MACRO

USING ACC-36E WITH POWER UMAC

USING ACC-36E WITH TURBO UMAC

 

But,how to setup ACC36E on UMAC MACRO STATION if the master station is PPMAC with ACC5E3 ?

 

In the slave side I have set that:

//ACC-36E on UMAC MACRO station

// Setting up the automatic read function for the 1st ACC-36E

MS0,MI987=1 // Enable automatic ADC read function (MACRO IC 0)

MS0,MI988=$FF//00 ; All 16 ADCs unipolar ;$FF ; All 16 ADCs bipolar

MS0,MI989=$8800 // Card base address

 

MS0,MI19=4 // MACRO Station I/O Data Transfer Period (adjustable)

MS0,MI975=$CCC // MACRO IC#0 I/O Node Enable, nodes 2, 3, 6, 7,10,11:10 for 1st 65E,11 for 2st 65E

MS0,MI173=$20C0A1000200 // 1st ACC-36E ADC1 thru ADC6 (lower 12 bits of $0200 thru $0205)

MS0,MI174=$20C0A9000200 // 1st ACC-36E ADC9 thru ADC14 (upper 12 bits of $0200 thru $0205)

MS0,MI175=$20C0A0000206 // 1st ACC-36E ADCs 7, 8, 15, 16 (lower + upper of $0206 thru $0207)

 

How to get the value in the PPMAC side?

 

Thanks a lot.

Link to comment
Share on other sites

  • Replies 2
  • Created
  • Last Reply

Top Posters In This Topic

Top Posters In This Topic

Hi,

 

Great question. We have not yet updated this manual with such information.

 

The setup on the MACRO Station side will be the same regardless of whether the Ring Controller/Master is a Turbo PMAC or Power PMAC. The main difference will simply be how you map your M-Variables as shown on pages 50, 53, 57, 59, and 60. Instead of pointing directly to MACRO registers in X memory as in Turbo PMAC, the M-Variables (or "ptr" variables) will point to Gate3.MacroInA[k] or Gate3.MacroInB[k] registers.

 

It is late in the day here now, but I can make up a table of these pointers for Power PMAC for you tomorrow morning.

Link to comment
Share on other sites

Page 50's table should look like this for PPMAC (page 57 maps the same):

 

// Unsigned ADC Values
ptr First36E_ADC(16)->*;
First36E_ADC(0)->Gate3[0].MacroInA[2][1].16.12;
First36E_ADC(1)->Gate3[0].MacroInA[2][2].16.12;
First36E_ADC(2)->Gate3[0].MacroInA[2][3].16.12;

First36E_ADC(3)->Gate3[0].MacroInA[3][1].16.12;
First36E_ADC(4)->Gate3[0].MacroInA[3][2].16.12;
First36E_ADC(5)->Gate3[0].MacroInA[3][3].16.12;

First36E_ADC(6)->Gate3[0].MacroInA[6][1].16.12;
First36E_ADC(7)->Gate3[0].MacroInA[6][2].16.12;
First36E_ADC(8)->Gate3[0].MacroInA[6][3].16.12;

First36E_ADC(9)->Gate3[0].MacroInA[7][1].16.12;
First36E_ADC(10)->Gate3[0].MacroInA[7][2].16.12;
First36E_ADC(11)->Gate3[0].MacroInA[7][3].16.12;

First36E_ADC(12)->Gate3[0].MacroInA[2][0].8.12;
First36E_ADC(13)->Gate3[0].MacroInA[3][0].8.12;
First36E_ADC(14)->Gate3[0].MacroInA[2][0].20.12;
First36E_ADC(15)->Gate3[0].MacroInA[3][0].20.12;

// Signed ADC Values
ptr First36E_ADC(16)->*;
First36E_ADC(0)->Gate3[0].MacroInA[2][1].16.12S;
First36E_ADC(1)->Gate3[0].MacroInA[2][2].16.12S;
First36E_ADC(2)->Gate3[0].MacroInA[2][3].16.12S;

First36E_ADC(3)->Gate3[0].MacroInA[3][1].16.12S;
First36E_ADC(4)->Gate3[0].MacroInA[3][2].16.12S;
First36E_ADC(5)->Gate3[0].MacroInA[3][3].16.12S;

First36E_ADC(6)->Gate3[0].MacroInA[6][1].16.12S;
First36E_ADC(7)->Gate3[0].MacroInA[6][2].16.12S;
First36E_ADC(8)->Gate3[0].MacroInA[6][3].16.12S;

First36E_ADC(9)->Gate3[0].MacroInA[7][1].16.12S;
First36E_ADC(10)->Gate3[0].MacroInA[7][2].16.12S;
First36E_ADC(11)->Gate3[0].MacroInA[7][3].16.12S;

First36E_ADC(12)->Gate3[0].MacroInA[2][0].8.12S;
First36E_ADC(13)->Gate3[0].MacroInA[3][0].8.12S;
First36E_ADC(14)->Gate3[0].MacroInA[2][0].20.12S;
First36E_ADC(15)->Gate3[0].MacroInA[3][0].20.12S;

 

 

Page 53 (page 60's mappings are the same):

 

// Unsigned ADC Values
ptr First36E_ADC(16)->*;
First36E_ADC(0)->Gate3[0].MacroInA[2][1].16.12;
First36E_ADC(1)->Gate3[0].MacroInA[2][2].16.12;
First36E_ADC(2)->Gate3[0].MacroInA[2][3].16.12;

First36E_ADC(3)->Gate3[0].MacroInA[3][1].16.12;
First36E_ADC(4)->Gate3[0].MacroInA[3][2].16.12;
First36E_ADC(5)->Gate3[0].MacroInA[3][3].16.12;

First36E_ADC(6)->Gate3[0].MacroInA[6][1].16.12;
First36E_ADC(7)->Gate3[0].MacroInA[6][2].16.12;
First36E_ADC(8)->Gate3[0].MacroInA[6][3].16.12;

First36E_ADC(9)->Gate3[0].MacroInA[7][1].16.12;
First36E_ADC(10)->Gate3[0].MacroInA[7][2].16.12;
First36E_ADC(11)->Gate3[0].MacroInA[7][3].16.12;

First36E_ADC(12)->Gate3[0].MacroInA[2][0].8.12;
First36E_ADC(13)->Gate3[0].MacroInA[3][0].8.12;
First36E_ADC(14)->Gate3[0].MacroInA[2][0].20.12;
First36E_ADC(15)->Gate3[0].MacroInA[3][0].20.12;

// Signed ADC Values
ptr First36E_ADC(16)->*;
First36E_ADC(0)->Gate3[0].MacroInA[2][1].16.12S;
First36E_ADC(1)->Gate3[0].MacroInA[2][2].16.12S;
First36E_ADC(2)->Gate3[0].MacroInA[2][3].16.12S;

First36E_ADC(3)->Gate3[0].MacroInA[3][1].16.12S;
First36E_ADC(4)->Gate3[0].MacroInA[3][2].16.12S;
First36E_ADC(5)->Gate3[0].MacroInA[3][3].16.12S;

First36E_ADC(6)->Gate3[0].MacroInA[6][1].16.12S;
First36E_ADC(7)->Gate3[0].MacroInA[6][2].16.12S;
First36E_ADC(8)->Gate3[0].MacroInA[6][3].16.12S;

First36E_ADC(9)->Gate3[0].MacroInA[7][1].16.12S;
First36E_ADC(10)->Gate3[0].MacroInA[7][2].16.12S;
First36E_ADC(11)->Gate3[0].MacroInA[7][3].16.12S;

First36E_ADC(12)->Gate3[0].MacroInA[2][0].8.12S;
First36E_ADC(13)->Gate3[0].MacroInA[3][0].8.12S;
First36E_ADC(14)->Gate3[0].MacroInA[2][0].20.12S;
First36E_ADC(15)->Gate3[0].MacroInA[3][0].20.12S;

// Unsigned ADC Values
ptr Second36E_ADC(16)->*;
Second36E_ADC(0)->Gate3[0].MacroInB[2][1].16.12;
Second36E_ADC(1)->Gate3[0].MacroInB[2][2].16.12;
Second36E_ADC(2)->Gate3[0].MacroInB[2][3].16.12;

Second36E_ADC(3)->Gate3[0].MacroInB[3][1].16.12;
Second36E_ADC(4)->Gate3[0].MacroInB[3][2].16.12;
Second36E_ADC(5)->Gate3[0].MacroInB[3][3].16.12;

Second36E_ADC(6)->Gate3[0].MacroInB[6][1].16.12;
Second36E_ADC(7)->Gate3[0].MacroInB[6][2].16.12;
Second36E_ADC(8)->Gate3[0].MacroInB[6][3].16.12;

Second36E_ADC(9)->Gate3[0].MacroInB[7][1].16.12;
Second36E_ADC(10)->Gate3[0].MacroInB[7][2].16.12;
Second36E_ADC(11)->Gate3[0].MacroInB[7][3].16.12;

Second36E_ADC(12)->Gate3[0].MacroInB[2][0].8.12;
Second36E_ADC(13)->Gate3[0].MacroInB[3][0].8.12;
Second36E_ADC(14)->Gate3[0].MacroInB[2][0].20.12;
Second36E_ADC(15)->Gate3[0].MacroInB[3][0].20.12;

// Signed ADC Values
ptr Second36E_ADC(16)->*;
Second36E_ADC(0)->Gate3[0].MacroInB[2][1].16.12S;
Second36E_ADC(1)->Gate3[0].MacroInB[2][2].16.12S;
Second36E_ADC(2)->Gate3[0].MacroInB[2][3].16.12S;

Second36E_ADC(3)->Gate3[0].MacroInB[3][1].16.12S;
Second36E_ADC(4)->Gate3[0].MacroInB[3][2].16.12S;
Second36E_ADC(5)->Gate3[0].MacroInB[3][3].16.12S;

Second36E_ADC(6)->Gate3[0].MacroInB[6][1].16.12S;
Second36E_ADC(7)->Gate3[0].MacroInB[6][2].16.12S;
Second36E_ADC(8)->Gate3[0].MacroInB[6][3].16.12S;

Second36E_ADC(9)->Gate3[0].MacroInB[7][1].16.12S;
Second36E_ADC(10)->Gate3[0].MacroInB[7][2].16.12S;
Second36E_ADC(11)->Gate3[0].MacroInB[7][3].16.12S;

Second36E_ADC(12)->Gate3[0].MacroInB[2][0].8.12S;
Second36E_ADC(13)->Gate3[0].MacroInB[3][0].8.12S;
Second36E_ADC(14)->Gate3[0].MacroInB[2][0].20.12S;
Second36E_ADC(15)->Gate3[0].MacroInB[3][0].20.12S;

Link to comment
Share on other sites

Guest
This topic is now closed to further replies.
 Share


×
×
  • Create New...