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ACC36E setup parameter can't be saved in PPMAC,Why


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I'm using PPower whith ACC-36E.

After setting OK and saved,the setting will lost after reset,why?

Should these parameter be setup once in PLC after PPMAC start?

//ACC-36E BE SET EVERY POWER CYCLY MUST

AdcDemux.Address[0] = $A00000

AdcDemux.Address[1] = $A00000

AdcDemux.Address[2] = $A00000

AdcDemux.Address[3] = $A00000

AdcDemux.Address[4] = $A00000

AdcDemux.Address[5] = $A00000

AdcDemux.Address[6] = $A00000

AdcDemux.Address[7] = $A00000

/**************** if bipolar , signed ********************/

// for bipolar ACC 36E

ADCDemux.ConvertCode[0] = $800800; // convert ADC's 1 & 9 from ADCDemux.Address[4]

ADCDemux.ConvertCode[1] = $900900; // convert ADC's 2 & 10 from ADCDemux.Address[5]

ADCDemux.ConvertCode[2] = $A00A00; // convert ADC's 3 & 11 from ADCDemux.Address[6]

ADCDemux.ConvertCode[3] = $B00B00; // convert ADC's 4 & 12 from ADCDemux.Address[7]

ADCDemux.ConvertCode[4] = $C00C00; // convert ADC's 5 & 13 from ADCDemux.Address[8]

ADCDemux.ConvertCode[5] = $D00D00; // convert ADC's 6 & 14 from ADCDemux.Address[9]

ADCDemux.ConvertCode[6] = $E00E00; // convert ADC's 7 & 15 from ADCDemux.Address[10]

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Hello,Steve

Thanks for you reply.

No problem "AdcDemux.Enable = 8" already.Can't be saved still.

 

I try very simple test.

1、$$$***;

2、save;

3、$$$

4、p2=1000

5、save

6、$$$

Then,ask for p2,

p2 is 0.

 

By the way,my PPMAC is totlly new.

 

It seems the flash of PPMAC have problem.But it totlly new.The firmware is 1.6.0.30.

problem_save.bmp

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I try another PPMAC CPU,the software version is 1.3.0.0,

same trying,same result,p2=0 after saved and $$$.

So, maybe it's not the CPU problem.But who's problem? The backplane?

 

My new PPmac system is :

 

Master:

POWER PMAC CPU

+ ACC-24E2S X 5

+ ACC-5E3(16 node)

+ ACC-36E

+ ACC-65E

+ ACC-R2

Slave:

16 Axis MACRO CPU-OPT-A

+ ACC-24E2S

+ ACC-36E

+ ACC-65E x 2

+ ACC-R1

 

And the ACC36Es and ACC24E2Ss works well both master and slave except PPmac CPU.ACC-65E on Master side work well,on the Slave side is tested now.

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The "AdcDemux" structures are saved setup elements but P-variables are not saved. Depending on how a PLC was sent to the POWER PMAC it may not be saved. If it was part of your current project it will be saved. If this PLC were sent on another communication thread outside the "download" feature of the IDE, it will be considered a transient program and will not be saved.
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New trying of New PPmac:

 

p1000 is same to p2,will lost;

plc1 will lost after save and $$$.

 

But,

prog2 will be saved corectly,and not lost after $$$.

 

Also, take a look at the "Hardware Diagnosis" screen of the "Power PMAC System Setup" does all of your hardware properly show up there?:

Capture.JPG.552502fb74e1b80ab2829c956fed3c74.JPG

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Yes,all hardware are there.Also all ACC24E2S and ACC65E and ACC36E and ACC5E3 works correctly in the Master Station.

Also all ACC24E2S and ACC36E works correctly in the SLAVE except ACC-65E,because I'm trying now.

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The paremeters about axis can be saved correctly.Likes:

i5113=5

 

Motor[1].ServoCtrl = 1

Motor[1].pDac = Gate1[4].Chan[0].Pwm[2].a

Motor[1].pLimits = 0

Gate1[4].Chan[0].EncCtrl = 8

Gate1[4].Chan[0].OutputMode = 3

Motor[1].Servo.Kvfb=10

 

The paremeters about Macro can be saved correctly.Likes:

Sys.WpKey=$AAAAAAAA;

//MACRO Communication Setup

Gate3[0].MacroEnableA=$FCCFF00; //Activate 4 Servo Nodes and 6 IO Nodes of MACRO A

Gate3[0].MacroModeA=$403000; // Set MACRO A as master

 

Macro.TestPeriod=100; //MACRO Ring Check Period (Equivalent of I80)

Macro.TestMaxErrors=2; //MACRO Maximum Ring Error Count (Equivalent of I81)

Macro.TestReqdSynchs=2; //MACRO Minimum Sync Packet Count (Equivalent of I82)

 

The defines can be saved correctly.Likes:

PTR S1_Output1->Gate3[0].MacroOutA[10][2].24.1;

PTR S1_Output2->Gate3[0].MacroOutA[10][2].25.1;

PTR S1_Output3->Gate3[0].MacroOutA[10][2].26.1;

PTR S1_Output4->Gate3[0].MacroOutA[10][2].27.1;

PTR S1_Output5->Gate3[0].MacroOutA[10][2].28.1;

PTR S1_Output6->Gate3[0].MacroOutA[10][2].29.1;

PTR S1_Output7->Gate3[0].MacroOutA[10][2].30.1;

PTR S1_Output8->Gate3[0].MacroOutA[10][2].31.1;

PTR S1_Output9->Gate3[0].MacroOutA[10][3].16.1;

PTR S1_Output10->Gate3[0].MacroOutA[10][3].17.1;

PTR S1_Output11->Gate3[0].MacroOutA[10][3].18.1;

PTR S1_Output12->Gate3[0].MacroOutA[10][3].19.1;

PTR S1_Output13->Gate3[0].MacroOutA[10][3].20.1;

PTR S1_Output14->Gate3[0].MacroOutA[10][3].21.1;

PTR S1_Output15->Gate3[0].MacroOutA[10][3].22.1;

PTR S1_Output16->Gate3[0].MacroOutA[10][3].23.1;

PTR S1_Output17->Gate3[0].MacroOutA[10][3].24.1;

PTR S1_Output18->Gate3[0].MacroOutA[10][3].25.1;

PTR S1_Output19->Gate3[0].MacroOutA[10][3].26.1;

PTR S1_Output20->Gate3[0].MacroOutA[10][3].27.1;

PTR S1_Output21->Gate3[0].MacroOutA[10][3].28.1;

PTR S1_Output22->Gate3[0].MacroOutA[10][3].29.1;

PTR S1_Output23->Gate3[0].MacroOutA[10][3].30.1;

PTR S1_Output24->Gate3[0].MacroOutA[10][3].31.1;

//SECOND ACC65E ON SLAVE

PTR S2_Input1->Gate3[0].MacroInA[11][1].16.1;

PTR S2_Input2->Gate3[0].MacroInA[11][1].17.1;

PTR S2_Input3->Gate3[0].MacroInA[11][1].18.1;

PTR S2_Input4->Gate3[0].MacroInA[11][1].19.1;

PTR S2_Input5->Gate3[0].MacroInA[11][1].20.1;

PTR S2_Input6->Gate3[0].MacroInA[11][1].21.1;

PTR S2_Input7->Gate3[0].MacroInA[11][1].22.1;

PTR S2_Input8->Gate3[0].MacroInA[11][1].23.1;

PTR S2_Input9->Gate3[0].MacroInA[11][1].24.1;

PTR S2_Input10->Gate3[0].MacroInA[11][1].25.1;

PTR S2_Input11->Gate3[0].MacroInA[11][1].26.1;

PTR S2_Input12->Gate3[0].MacroInA[11][1].27.1;

PTR S2_Input13->Gate3[0].MacroInA[11][1].28.1;

PTR S2_Input14->Gate3[0].MacroInA[11][1].29.1;

PTR S2_Input15->Gate3[0].MacroInA[11][1].30.1;

PTR S2_Input16->Gate3[0].MacroInA[11][1].31.1;

PTR S2_Input17->Gate3[0].MacroInA[11][2].16.1;

PTR S2_Input18->Gate3[0].MacroInA[11][2].17.1;

PTR S2_Input19->Gate3[0].MacroInA[11][2].18.1;

PTR S2_Input20->Gate3[0].MacroInA[11][2].19.1;

PTR S2_Input21->Gate3[0].MacroInA[11][2].20.1;

PTR S2_Input22->Gate3[0].MacroInA[11][2].21.1;

PTR S2_Input23->Gate3[0].MacroInA[11][2].22.1;

PTR S2_Input24->Gate3[0].MacroInA[11][2].23.1;

 

PTR S2_Output1->Gate3[0].MacroOutA[11][2].24.1;

PTR S2_Output2->Gate3[0].MacroOutA[11][2].25.1;

PTR S2_Output3->Gate3[0].MacroOutA[11][2].26.1;

PTR S2_Output4->Gate3[0].MacroOutA[11][2].27.1;

PTR S2_Output5->Gate3[0].MacroOutA[11][2].28.1;

PTR S2_Output6->Gate3[0].MacroOutA[11][2].29.1;

PTR S2_Output7->Gate3[0].MacroOutA[11][2].30.1;

PTR S2_Output8->Gate3[0].MacroOutA[11][2].31.1;

PTR S2_Output9->Gate3[0].MacroOutA[11][3].16.1;

PTR S2_Output10->Gate3[0].MacroOutA[11][3].17.1;

PTR S2_Output11->Gate3[0].MacroOutA[11][3].18.1;

PTR S2_Output12->Gate3[0].MacroOutA[11][3].19.1;

PTR S2_Output13->Gate3[0].MacroOutA[11][3].20.1;

PTR S2_Output14->Gate3[0].MacroOutA[11][3].21.1;

PTR S2_Output15->Gate3[0].MacroOutA[11][3].22.1;

PTR S2_Output16->Gate3[0].MacroOutA[11][3].23.1;

PTR S2_Output17->Gate3[0].MacroOutA[11][3].24.1;

PTR S2_Output18->Gate3[0].MacroOutA[11][3].25.1;

PTR S2_Output19->Gate3[0].MacroOutA[11][3].26.1;

PTR S2_Output20->Gate3[0].MacroOutA[11][3].27.1;

PTR S2_Output21->Gate3[0].MacroOutA[11][3].28.1;

PTR S2_Output22->Gate3[0].MacroOutA[11][3].29.1;

PTR S2_Output23->Gate3[0].MacroOutA[11][3].30.1;

PTR S2_Output24->Gate3[0].MacroOutA[11][3].31.1;

//ACC-36E ON MASTER

#define ADC1 AdcDemux.ResultLow[0] //ADC1

#define ADC2 AdcDemux.ResultLow[1] //ADC2

#define ADC3 AdcDemux.ResultLow[2] //ADC3

#define ADC4 AdcDemux.ResultLow[3] //ADC4

#define ADC5 AdcDemux.ResultLow[4] //ADC5

#define ADC6 AdcDemux.ResultLow[5] //ADC6

#define ADC7 AdcDemux.ResultLow[6] //ADC7

#define ADC8 AdcDemux.ResultLow[7] //ADC8

#define ADC9 AdcDemux.ResultHigh[0] //ADC9

#define ADC10 AdcDemux.ResultHigh[1] //ADC10

#define ADC11 AdcDemux.ResultHigh[2] //ADC11

#define ADC12 AdcDemux.ResultHigh[3] //ADC12

#define ADC13 AdcDemux.ResultHigh[4] //ADC13

#define ADC14 AdcDemux.ResultHigh[5] //ADC14

#define ADC15 AdcDemux.ResultHigh[6] //ADC15

#define ADC16 AdcDemux.ResultHigh[7] //ADC16

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